Referring now to FIG. 1, a functional circuit diagram of a differential resistance ladder for an analog to digital converter (ADC) is presented. The differential resistance ladder includes a positive leg 100 and a negative leg 101, which respectively receive a positive phase and a negative phase of an input signal. The positive leg 100 includes a first voltage source 102 that outputs an AC voltage equal to the positive phase (V+) of the input signal, referenced to a ground potential 104. This voltage is applied to a first terminal of a first resistance 106 including resistances 106-1, 106-2, . . . , and 106-N. An opposite terminal of the first resistance 106 communicates with a first terminal of a second resistance 108 including resistances 108-1, 108-2, . . . , and 108-N. An opposite terminal of the second resistance 108 communicates with a second voltage source 110. The second voltage source 110 outputs a voltage equal to V+ minus a DC voltage (VDC), referenced to ground 104.
The negative leg 101 includes a third voltage source 112 that outputs an AC voltage equal to the negative phase (V_) of the input signal to a first terminal of a third resistance 114 including resistances 114-1, 114-2, . . . , and 114-N. An opposite terminal of the third resistance 114 communicates with a first terminal of a fourth resistance 116 including resistances 116-1, 116-2, . . . , and 116-N. An opposite terminal of the fourth resistance 116 communicates with a fourth voltage source 118. The fourth voltage source 118 outputs a voltage equal to V− minus the DC voltage (VDC), referenced to ground. The first and second resistances 106 and 108 are generally comprised of a number (often a power of two) of smaller resistances. Also, the third and fourth resistances 114 and 116 are often comprised of a number of smaller resistances. For a linear ADC, the number of smaller resistances that define each of the resistances 106, 108, 114, and 116 will generally be equal.
Referring now to FIG. 2, a functional circuit diagram of an alternative differential resistance ladder configuration according to the prior art is presented. The differential resistance ladder includes a positive leg 136 and a negative leg 138, which respectively receive a positive phase and a negative phase of an input signal. The positive leg 136 includes a first voltage source 140 that outputs a voltage equal to the positive phase (V+) of the input signal, referenced to ground. This voltage is applied to a first terminal of a first resistance 142 including resistances 142-1, 142-2, . . . , and 142-N. An opposite terminal of the first resistance 142 communicates with a first terminal of a second resistance 144 including resistances 144-1, 144-2, . . . , and 144-N and with a second voltage source 146. The second voltage source 146 outputs a voltage equal to V+ minus half of a DC voltage (VDC), referenced to ground. An opposite terminal of the second resistance 144 communicates with a third voltage source 148, which outputs a voltage equal to V+ minus VDC, referenced to ground.
The negative leg 138 includes a fourth voltage source 150 that outputs a voltage equal to the negative phase (V−) of the input signal, referenced to ground. The fourth voltage source 150 communicates with a first terminal of a first resistance 152 including resistances 152-1,152-2, . . . , and 152-N. An opposite terminal of the third resistance 152 communicates with a first terminal of a fourth resistance 154 including resistances 154-1, 154-2, . . . , and 154-N and with a fifth voltage source 156. The fifth voltage source 156 outputs a voltage equal to V− minus VDC/2, referenced to ground. An opposite terminal of the fourth resistance 154 communicates with a sixth voltage source 158, which outputs a voltage equal to V− minus VDC, referenced to ground.
The resistances 142, 144, 152, and 154 are each often composed of a number of smaller resistances (generally an equal number for a linear ADC). The configuration of FIG. 2 is similar to that of FIG. 1, with the addition of the second and fifth voltage sources 146 and 156. The second voltage source 146 is connected to the center node, the node between the first and second resistances 142 and 144. Without the second voltage source 146, the center node would receive the input signal last, being equidistant from the driving voltage sources 140 and 148. The addition of the second voltage source 146 removes delay from this node. The greatest delay is now in the midpoint of the first resistance 142 and the midpoint of the second resistance 144. These midpoints experience only one quarter of the RC delay that the center node had previously, being half as far from the driving voltage sources 140 and 146. The same modification is made to the negative leg 138, adding the fifth voltage source 156 to the node that would otherwise experience the greatest delay.